FPGAs are integrated circuits that include logic, processing, memory, and routing resources that may be programmed in the field after manufacture. FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. At certain processing edges and operating conditions in FPGAs, the delay of falling edge signals, where a signal transitions from Vcc to ground (1 to 0), is often not the same as the delay of rising edge signals, where a signal transitions from ground to Vcc (0 to 1). This is due to the fact that in current CMOS processes the delay through a PMOS device is typically higher than the delay through an NMOS device. The differences in delay of rising and falling edge signals may pose to be a problem in instances where a signal though an FPGA transitions through an unbalanced number of rising and falling edges along a path. This could result in a propagation delay of the signal that is either much shorter or longer than expected.
One circuit design technique that has been used to address this problem involves changing the relative sizes of the PMOS and NMOS devices to equalize the delay of rising edge and falling edge signals under typical process and operating conditions, such as temperature and operating voltage. This approach, however, was effective at best only under selective processes and operating conditions. It was found that under other process corners and other operating conditions, the delay of rising and falling edge signals in a device could still be different and result in the same problem. Furthermore, this circuit design techniques suffered the additional drawback of increasing the average delay through a circuit, which is undesirable.
Thus, what is needed is an efficient method and apparatus for optimizing delay paths through FPGAs.